The present invention relates to a method of programming a non-volatile memory device. More particularly, the present invention relates to a method of programming a non-volatile memory device for enhancing a channel boosting of a bit line of which programming is inhibited.
The demand has increased for a non-volatile memory device that electrically programs and erases data, wherein data is not erased even though power is not supplied to the non-volatile memory device.
A technique for highly integrating a memory cell has been developed to manufacture a mass storage memory device for storing a large amount of data.
This technique has been applied to NAND flash memory devices that includes a memory cell array having a plurality of cell strings, wherein memory cells are connected in serial in one cell string.
A memory cell in a flash memory device generally includes a gate, in which a tunnel insulating layer, a floating gate, a dielectric layer and a control gate are laminated on a semiconductor substrate, and a junction area formed to both sides of the gate on the semiconductor substrate. The memory device is programmed by injecting hot electrons into the floating gate, and is erased by discharging the injected hot electrons through an F-N tunneling.
FIG. 1 is a timing diagram illustrating voltages applied to word lines so as to program a flash memory device.
In FIG. 1, the flash memory device for performing a program operation includes a first word line WL<0> to a thirty-second word line WL<31>. Here, in case that the thirtieth word line WL<29> is selected for the program operation, a program voltage Vpgm is applied to the thirtieth word line WL<29>. In addition, a second pass voltage Vpass2 is applied to a thirty-first word line WL<30> and the thirty-second word line WL<31>, and a first pass voltage Vpass1 is provided to the first word line WL<0> to a twenty-ninth word line WL<28>.
The program operation is performed by injecting electrons in a channel region to the floating gate through a Fowler-Nordheim F-N tunneling due to high voltage difference of the channel region and the control gate in a selected memory cell, wherein the high voltage difference is generated by applying a voltage of 0V to a selected bit line and providing the program voltage Vpgm to a selected word line.
However, since the program voltage Vpgm is applied to non-selected memory cells as well as the selected memory cell disposed along the same word line, the non-selected memory cells are programmed.
This phenomenon is referred to as a program disturbance. To prevent this program disturbance, a source of a drain select transistor DST in a cell string having the non-selected memory cell connected to the selected word line and a non-selected bit line is charged to a level of (Vcc−Vth), Vcc is a power supply voltage and Vth is a threshold voltage of the drain select transistor DST, the program voltage Vpgm is applied to the selected word line, and the pass voltage Vpass is provided to the non-selected word line. As a result, a channel voltage Vch of the memory cells in the same cell string is boosted, and so the non-selected memory cell is not programmed.
A non-volatile memory device uses usually a sequential method of performing a program operation in a direction to the thirty-second word line WL<31> adjacent to a drain select line from the first word line WL<0> adjacent to a source select line.
Accordingly, in case that the twenty-ninth word line WL<28> is programmed in the program operation, a corresponding memory cell is not fully turned on by the first pass voltage Vpass 1, and so the channel voltage Vch is not adequately boosted. As a result, a disturbance phenomenon, that a non-selected memory cell is programmed, may be generated.